با سلام بنده یک متنیو مطالعه میکردم و تو فهمش دچار مشکل شدم.منطورش از این که زمانی یک بیت ۴ حالته به ۲ حالته تبدیل می شود بیت های ناشناخته یا امپدانس بالا باید به صفر تبدیل شوند چیه؟؟
Verilog has reg and wire data-types to describe hardware behavior. Since verification of hardware can become more complex and demanding, datatypes in Verilog are not sufficient to develop efficient testbenches and testcases. Hence System Verilog has extended Verilog by adding more C like data-types for better encapsulation and compactness.

Types that can have unknown and high-impedance value are called 4-state types. In a typical verification testbench, there are many cases where we don't really need all the four values (0, 1, x, z) like for example when modeling a network packet with a header that specifies the length of the packet. System Verilog adds many new 2-state data types that can only store and have a value of either 0 or 1. This will aid in faster simulation, take less memory and are preferred in some design styles. When a 4-state value is converted to a 2-state value, any unknown or high-impedance bits shall be converted to zeros